Designing integrated circuit (IC) devices such as microprocessors, memory devices, logic devices, radio frequency identification (RFID) tags, etc. can include: production of the initial circuit design schematic, electrical simulation of the circuit design to verify proper functionality, conversion of the circuit schematic into a three dimensional physical translation or graphical representation of the schematic devices, verification that the physical device translation is analogous to the circuit design and will provide a functioning device, failure analysis, and optimization of circuit and physical designs to ensure device reliability, stability, and manufacturability.
Computer aided design (CAD) software tools and other electronic design automation (EDA) tools are used for all stages of IC design. Design tools from several different vendors are currently used in the semiconductor industry, including Cadence® (Cadence Design Systems, Inc., San Jose, Calif.), Knights Camelot™ (Magma® Design Automation, San Jose, Calif.), and SPICE (SiSoft, Maynard, Mass.), as well as other design environments.
One goal in IC manufacture is to faithfully reproduce the original IC design on a semiconductor chip or wafer. However, as the size of IC devices is reduced and the device density increases, variability between components built on the semiconductor chip becomes problematic. Additionally, as high levels of strain are introduced to IC technologies to boost performance, such component variations (also referred herein as “context variations”) as well as parameter shifts may further increase. Consequently, the context variations can cause the circuit corresponding to the design or layout to behave differently than expected when embodied on the semiconductor chip. For example, during IC manufacturing processes, analog components can be significantly degraded by context variations because many analog designs require tight tolerances and very good matching between components. Consequently, the degraded analog components can be non-functional.
Conventional solutions to address the context variations involve characterizing and including the context variations in component models as for digital/logic designs, but without reducing the variations.
Thus, there is a need to overcome these and other problems of the prior art and to provide a design method and design kit for reducing or minimizing context variations in IC processes through design rule restrictions.